The present invention relates, in general, to the field of data processors and methods. More particularly, the present invention relates to an output compare system and method for a microprocessor or microcomputer having a timer output compare force register by which any combination of specified output compare actions may be implemented even if the output compare value does not equal the counter value.
In former MPU and MCU systems, there have been provided output compare functions to generate a timed output signal from the device. Such output signals could be used to either (1) set the output, (2) clear the output, (3) toggle the output, or (4) indicate no change to the output. In implementing this output compare function, it has formerly been necessary to initiate a 16 bit read of the MPU/MCU counter present value, add a 16 bit value to compensate for the required software, and finally write a 16 bit number to the compare register so that a normal compare operation would subsequently result. Implementing an output compare function by means of software resulted in uncertainty with regard to output pulse synchronization, as well as requiring substantial program space and introducing increased latency to the desired output action.